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LTC3765 1 3765f typical application features description active clamp forward controller and gate driver the ltc ? 3765 is a start-up controller and gate driver for use in a self-starting secondary-side control forward converter. when combined with the ltc3766 secondary- side synchronous forward controller, a complete isolated power supply is created using a minimum of discrete parts. a proprietary scheme is used to multiplex gate drive signals and bias power across the isolation barrier through a small pulse transformer. the LTC3765 contains an on-chip bridge rectifier that extracts gate drive bias power from this pulse transformer, eliminating the need for a separate bias supply. a precision undervoltage lockout circuit and linear regulator controller ensure a quick and well-controlled start-up. the LTC3765 includes an active clamp output for driving an external pmos, as well as an adjustable delay to optimize efficiency. the active clamp architecture reduces voltage stress on the main power switch, and provides the highest possible efficiency. overcurrent protection and the direct flux limit guarantee no transformer saturation without compromising transient response. 36v-72v to 5v/15a active clamp isolated forward converter applications n supports self-starting secondary-side control n direct flux limit? guarantees no saturation n active clamp drive with delay adjustment n on-chip bridge rectifier eliminates need for separate gate drive bias supply n wide input supply range: 8v and up (limited only by external components) n linear regulator controller for fast start-up n high speed gate drivers n precision uvlo with adjustable hysteresis n overcurrent protection n overtemperature protection n adjustable start-up frequency and soft-start n tiny 16-lead msop package n isolated battery chargers n isolated 48v telecommunication systems n servers and embedded computing n automotive and heavy equipment l , lt, ltc, ltm, polyphase, linear technology and the linear logo are registered trademarks and direct flux limit, thinsot and no r sense are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7200014 and 6144194. other patents pending. fg i s ? i s + pt + fb ith pt ? ss sw sg gnd pgnd sgd fgd mode run v in ndrv ltc3766 v cc run si3437dv (sot-23) 15m 0.5w 3m 2w v cc in + in ? fs/uv ssflt ndrv pg r core delay sgnd 14k 18.2k 100 100 l1: pulse pa1393.152 t1: pulse pa0810 t2: pulse pa0297 15k 26.1k 33nf 22k 17.8k 3765 ta01 604 4.42k 0.1f t2 2:1 t1 6:2 10.5k 15k 365k 1/8w i pk 100k si3440dv v in ? v in + 36v to 72v fdms86201 bsc0901ns ?? sir414dp 33nf 4.7f LTC3765 pgnd i s + i s ? ag 1 168 i smag fs/sync v s + v s ? 1.0f 1nf 2.2nf 250vac 33nf 200v 47pf 470pf 2.2f 100v 3 220f 6.3v 2 l1 1.4h v out + 5v 15a v out ? 100nf 200v ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 2 3765f pin configuration absolute maximum ratings v cc , ndrv voltages ................................... C0.3v to 15v (ndrv-v cc ) voltage ..................................... C0.3v to 6v in + , in C , ssflt voltages ............................ C0.3v to 15v i smag voltage ................................................ C5v to 18v run voltage ................................................ C0.3v to 12v del ay, r core , fs/uv, i s + , i s C voltages ....... C0.3v to 6v operating junction temperature range (notes 2, 3) LTC3765e,LTC3765i .......................... C40c to 125c LTC3765h .......................................... C40c to 150c LTC3765mp ....................................... C55c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 5 6 7 8 pgnd pg v cc ag i smag delay i s ? i s + 16 15 14 13 12 11 10 9 in ? in + ndrv ssflt run r core fs/uv sgnd top view 17 sgnd mse package 16-lead plastic msop t jmax = 150c, ja = 45c/w, jc = 10c/w exposed pad (pin 17) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3765emse#pbf LTC3765emse#trpbf 3765 16-lead plastic msop C40c to 125c LTC3765imse#pbf LTC3765imse#trpbf 3765 16-lead plastic msop C40c to 125c LTC3765hmse#pbf LTC3765hmse#trpbf 3765 16-lead plastic msop C40c to 150c LTC3765mpmse#pbf LTC3765mpmse#trpbf 3765 16-lead plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v unless otherwise noted. symbol parameter conditions min typ max units v cc supply v ccop operating voltage range 7.7 14.5 v v ccuv v cc undervoltage lockout v cc rising v cc falling hysteresis l l 7.1 6.7 7.4 7.0 400 7.7 7.3 v v mv v cclr linear regulator output voltage (note 4) 8.0 8.5 9.0 v t r(vcc) rise time of v cc 35 s i cp ndrv charge pump output current v cc = 5v, v ndrv = 8v 35 a i cc dc supply current v run = 1.5v (note 5) 1.7 ma v rf rectifier total forward drop i cc = 25ma (note 6) 1 v run control/undervoltage lockout (run) v run run pin threshold v run rising v run falling l l 1.22 1.17 1.25 1.20 1.28 1.23 v v i hyst run pin hysteresis current v run = 1v l 4.0 5.0 6.0 a i run run pin leakage current v run = 1.5v C10 0 10 na www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 3 3765f electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v unless otherwise noted. symbol parameter conditions min typ max units gate drivers (pg, ag, delay) v ohpg pg high output voltage i pg = C100ma 11 v i pupg pg peak pull-up current 2.5 a r pdpg pg pull-down resistance i pg = 100ma 1.3 t rpg pg rise time 20% to 80%, c pg = 4.7nf 20 ns t fpg pg fall time 20% to 80%, c pg = 4.7nf 20 ns r puag ag pull-up resistance i ag = C10ma 12 r pdag ag pull-down resistance i ag = 10ma 9 t dag ag turn-on delay time 180 ns t dpg pg turn-on delay time r delay = 0 r delay = 10k r delay = 50k 120 390 40 140 460 160 530 ns ns ns oscillator (fs/uv) and soft-start (ssflt) f osc oscillator frequency r fs = 75k r fs = 10k 75 430 khz khz dc max oscillator maximum duty cycle v ssflt = 3.5v 70 % v fsuvh fs/uv output high v run = 1v 5 v i fsuv fs/uv pull-up current v run = 1v, v fs/uv = 1.5v 50 a i ss(c) soft-start charge current v run = 1.3v, v ssflt = 1v v run = 3.75v, v ssflt = 1v C4 C1.6 a a i ss(d) soft-start discharge current timing out after fault, v ssflt = 2v 1.25 a v flth fault output high v cc = 6.8v 5.75 6.5 v v fltd fault detection voltage 5 5.5 v overcurrent (i s + , i s C ) and direct flux limit (i smag , r core ) v is overcurrent threshold v isth = v is + Cv is C l 130 150 170 mv v ismag C i smag limit negative threshold relative to sgnd or v cc C1.15 C1 C0.85 v v ismag + i smag limit positive threshold relative to sgnd or v cc 0.85 1 1.15 v m ismag i smag replicated slope r core = 50k, v run = 1.25v r core = 50k, v run = 6.25v r core = 10k, v run = 1.25v r core = 10k, v run = 6.25v 75 375 335 1700 mv/s mv/s mv/s mv/s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3765 is tested under pulsed-load conditions such that t j t a . the LTC3765e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3765i is guaranteed over the C40c to 125c operating junction temperature range, the LTC3765h is guaranteed over the C40c to 150c operating junction temperature range and the LTC3765mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperature greater than 125c. the junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) according to the formula: t j = t a + (p d ? 45c/w) note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the linear regulator output voltage is measured with a vishay siliconix si3440dv n-channel mosfet external pass device. note 5: i cc is the sum of current into ndrv and v cc . note 6: rectifier forward voltage drop is the sum of the drop across the rectifier diode and synchronous switch. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 4 3765f typical performance characteristics charge pump output current vs temperature start-up oscillator frequency vs r fs resistor value start-up oscillator frequency vs temperature i smag thresholds vs temperature v cc supply current vs supply voltage i smag replicated slope vs run pin voltage and r core v cc uvlo thresholds vs temperature i smag replicated slope vs temperature charge pump output current vs v cc supply current supply voltage (v) 0 supply current (ma) 1.0 15 3765 g01 0.5 0 5 10 1.5 2.0 temperature (c) ?55 uvlo threshold (v) 7.1 7.3 155 3765 g02 6.9 6.8 5 65 125 ?25 35 95 7.6 7.0 7.2 7.4 7.5 falling rising v cc voltage (v) 3 0 charge pump current (a) 10 20 30 40 5 7 9 3765 g03 50 60 70 80 90 100 4 6 8 ndrv = v cc + 2v ndrv = v cc + 4v ?55 155 5 65 125 ?25 35 95 temperature (c) 20 charge pump current (a) 25 30 35 40 3765 g04 45 50 ndrv = 7v v cc = 5v ndrv = 9v r fs (k) 0 0 frequency (khz) 50 150 200 250 500 350 20 40 50 3765 g05 100 400 450 300 10 30 60 70 80 temperature (c) ?55 frequency (khz) 300 400 500 65 3765 g06 200 100 250 350 450 150 50 0 ?25 5 35 95 125 155 r fs = 10k r fs = 20k r fs = 75k temperature (c) ?55 threshold voltage magnitude (v) 1.01 1.02 1.03 35 95 3765 g07 1.00 0.99 ?25 5 65 125 155 0.98 0.97 positive threshold magnitude negative threshold magnitude run pin voltage (v) 1 0 replicated slope (mv/s) 200 600 800 1000 5 1800 3765 g08 400 3 2 6 4 7 1200 1400 1600 r core = 10k r core = 30k r core = 50k temperature (c) ?55 0 replicated slope (mv/s) 50 150 200 250 500 350 5 65 95 3765 g09 100 400 450 300 ?25 35 125 155 v run = 1.5v r core = 10k r core = 30k r core = 50k www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 5 3765f typical performance characteristics pg rising delay time vs delay pin resistor pg rising delay time vs temperature ag falling delay time vs temperature pg peak pull-up current vs temperature pg pull-down resistance vs temperature ag on-resistance vs temperature delay resistor (k) delay (ns) 3765 g10 1000 100 10 1 10 100 1000 0 100 200 300 400 500 600 700 temperature (c) ?55 delay (ns) 155 3764 g11 5 65 125 ?25 35 95 r delay = 22k r delay = 50k r delay = 10k 150 160 170 180 190 200 temperature (c) ?55 delay (ns) 155 3765 g12 5 65 125 ?25 35 95 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 temperature (c) ?55 peak current (a) 155 3765 g13 5 65 125 ?25 35 95 v cc = 12v 0 0.5 1.0 1.5 2.0 2.5 temperature (c) ?55 on-resistance () 155 3765 g14 5 65 125 ?25 35 95 v cc = 12v 0 5 10 15 20 25 temperature (c) ?55 on-resistance () 155 3765 g15 5 65 125 ?25 35 95 v cc = 12v pull-down pull-up pg output high voltage vs v cc supply voltage pg pull-down resistance vs v cc supply voltage ag on-resistance vs v cc supply voltage 7 8 9 10 11 12 13 14 15 v cc voltage (v) 8 pg output high (v) 15 3765 g16 10 12 14 9 11 13 i pg = ?100ma i pg = ?1ma 1.0 1.1 1.2 1.3 1.4 1.5 1.6 v cc voltage (v) 8 on-resistance () 15 3765 g17 10 12 14 9 11 13 8 9 10 11 12 13 14 15 16 v cc voltage (v) 8 on-resistance () 15 3765 g18 10 12 14 9 11 13 pull-down pull-up www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 6 3765f pin functions pgnd (pin 1): power ground. ground return for the high current gate drivers. pg (pin 2): primary gate. gate drive for the primary switch nmos. v cc (pin 3): main supply pin. a ceramic bypass capacitor should be tied between this pin and ground. ag (pin 4): active gate. gate drive for the active clamp pmos. this drive output is in phase with the pg out - put. connect to the gate of a pmos through a capacitive level-shift circuit. i smag (pin 5): magnetizing current sense pin. connect to a current sense resistor in series with the source of the active clamp pmos. this pin limits the magnetizing current of the main transformer to prevent core saturation when the active clamp is on. delay (pin 6): primary gate rising delay adjustment. a resistor from this pin to ground sets the ag rising to pg rising dead time, which is critical for optimizing efficiency. i s C , i s + (pin 7, pin 8): inputs to the overcurrent compara - tor. connect across a current sense resistor in series with the source of the primary nmos. fs/uv (pin 10): oscillator frequency set and undervoltage indicator. a resistor to ground sets the switching frequency during start-up. when the run pin is low, the v cc sup- ply is undervoltage, or the overtemperature protection is active, a 50a current source pulls this pin to the lesser of v cc and 5v as an indicator. r core (pin 11): transformer core saturation limit. a resistor from r core to ground proportional to transformer core parameters internally replicates the magnetizing cur - rent slope when the primary nmos is on. this slope in combination with the voltage on the i smag and run pins limits the on-time of the nmos to prevent saturation. see applications information. run (pin 12): run control and undervoltage lockout (uvlo). connect to a resistor divider to monitor the input voltage v in , which is required for proper operation of the direct flux limit. converter operation is enabled for v run ?>?1.25v. hysteresis is a fixed 50mv with an additional 5a hysteresis current that combines with the resistor divider to comprise the total uvlo hysteresis voltage. ssflt (pin 13): combination soft-start and fault indicator. a capacitor to ground sets the duty cycle ramp-up rate during primary-side start-up. to indicate a fault, the ssflt pin is momentarily pulled above 6v. ndrv (pin 14): drive for external linear regulator. con - nect to the gate of an nmos and connect a pull-up resistor to the main input voltage, v in . an internal charge pump drives this pin above v in for low input voltage applications. in + , in C (pin 15, pin 16): inputs from pulse transformer. connect through a dc restoring capacitor to the output winding of a pulse transformer. the input winding of the pulse transformer is driven by the ltc3766. after perform - ing an initial open-loop start-up, the LTC3765 detects and decodes pulse encoded pwm information at these pins, and then turns control of the pg and ag switching over to the ltc3766 secondary-side controller. additionally, an internal bridge rectifier on the in + /in C pins extracts dc power from the pulse transformer and delivers it to the v cc pin. sgnd (pin 9, exposed pad pin 17): signal ground. the exposed pad metal of the package provides good thermal contact to the printed circuit board. it must be soldered to a ground plane for rated thermal performance. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 7 3765f block diagram + ? + v cc ag 1v pgnd v cc uv v cc run control 7.4v/7.0v ndrv v in 1.25v/1.20v v cc v cc sgnd sgnd v cc i smag 4 pg pgnd uv fault v cc 2 pgnd 1 i s + i s ? 3765 bd 8 7 delay v in 6 r core 5 + ? + 150mv overcurrent comparator + ? + ? + ? + 1v logic ramp slope replicator soft-start fault oscillator soft-start pwm pwm decoder temperature monitor v cc undervoltage lockout linear regulator main pwm rectifier regulator shutdown 11 in + 15 in ? 16 14 v cc 3 sgnd 9 sgnd 17 run 5a v in 12 ? ? ? ? v cc v cc v cc 8.5v ? + ? + charge pump 50a fs/uv 5v 10 ssflt 13 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 8 3765f timing diagram v in + ? v in ? v in v in ? 0v LTC3765 ag LTC3765 pg swp node pulse encoded pwm v in 1 ? duty cycle ~ 0v set by ltc3766 fgd pin set by LTC3765 delay pin pwm on time set by ltc3766 sgd pin fixed 180ns delay 0v ltc3766 sg ltc3766 fg sw node swb node n s n p v out 1 ? duty cycle ~ 3765 td01 ? ? ag ag pg pg swp in + in ? LTC3765 ? ? 3765 f01 sg v out + v out ? v in + v in ? sw swb sw fg pt + fg pt ? sg ltc3766 figure 1. reference schematic for timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 9 3765f operation the LTC3765 is a forward converter start-up controller and gate driver for use in a single-switch forward converter with active clamp reset. when connected through a pulse transformer to the ltc3766 secondary-side synchronous forward controller, it forms a highly efficient forward con - verter with secondary-side regulation, galvanic isolation between input and output, and synchronous rectification. the LTC3765 and ltc3766 bias voltages are generated from a proprietary self-starting architecture which eliminates the need for an additional bias supply. linear regulator the LTC3765 features an external series pass linear regulator controller that eliminates the long start-up time associated with a conventional trickle charger. the ndrv pin regulates the gate of an external nmos transistor to ramp up the v cc supply with a well controlled 35s ramp time to the 8.5v regulation point. for low input supply voltage applications where the threshold of the external nmos transistor limits the v cc voltage, an internal charge pump boosts ndrv to a voltage higher than v in so that the external nmos can be fully enhanced. self-starting start-up when power is first applied and when the run pin and v cc have satisfied their respective start-up requirements, the LTC3765 begins open-loop operation using its own internal oscillator. power is supplied to the secondary by switching the gate drivers with a gradually increasing duty cycle from 0% to 70% as controlled by the rate of rise of the voltage on the ssflt pin. a peak charge circuit powered from an auxiliary winding off of the main transformer al - lows the ltc3766 to begin operation even for small duty cycles. when the ltc3766 has adequate voltage to satisfy its start-up requirements, it provides duty cycle informa - tion through the pulse transformer as shown in figure 2. the LTC3765 detects this signal and transfers control of the gate drivers to the ltc3766. the LTC3765 turns off the linear regulator and, through an on-chip rectifier, also extracts power from this signal. gate drive encoding the ltc3766 secondary-side forward controller sends a pulse-encoded signal through a small pulse transformer and series dc restore capacitor to the in + and in C pins of the LTC3765. after a brief start-up sequence to establish a communication lock between the two parts, the LTC3765 extracts clock and duty cycle information from the signal and uses it to control the pg and ag gate driver outputs. figure 2 shows how the ltc3766 drives the pulse trans - former in a complementary fashion, with a duty cycle of 79%. at the appropriate time during the positive cycle, the ltc3766 applies a short (150ns) zero voltage pulse across the pulse transformer, indicating the end of the pg on time. duty cycle = 15% duty cycle = 0% 150ns 150ns 3765 f02 1 clk per 1 clk per v in + ? v in ? figure 2. gate drive multiplexing scheme gate drivers and delay adjustment the active clamp gate driver (ag) and the primary switch gate driver (pg) are in-phase, with a programmable overlap time set by the delay pin. in an active clamp forward converter topology, the delay time between the active clamp pmos turn-off and the primary switch nmos turn-on is critical for optimizing efficiency. when the active clamp is on, the drain of the primary nmos, or primary switch node (swp), is driven to a voltage of approximately v in /(1 C duty cycle) by the main transformer. when the active clamp turns off, the current in the magnetizing inductance of the transformer ramps this voltage linearly down to v in . transitional power loss in the primary switch is minimized by turning it on when this voltage is at a minimum. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 10 3765f operation the delay time between the primary switch turn-off and the active clamp turn-on is substantially less critical. relative to the power loss due to turning on the primary switch, the power loss from switching the active clamp is significantly less. this difference results from both the lower current that the active clamp switches and the natural resonance of the system which facilitates zero voltage switching. when the primary switch turns off, the main transformer leakage inductance is biased with the peak ripple current of the inductor reflected through the transformer. this current drives the voltage across the active clamp pmos quickly to 0v. turning on the pmos after this transition results in minimal switching power loss. the LTC3765 active clamp turn on delay is internally fixed to 180ns. v in undervoltage lockout the run pin of the LTC3765 has precise thresholds and programmable hysteresis, which allows it to be used as an accurate voltage monitor on the input supply. an external resistive divider from v in to the run pin ensures that operation is disabled when v in is too low. additionally, when the run pin is below its threshold, a 5a current is pulled by the pin. this current, combined with the external resistive divider, increases the hysteresis beyond the internal minimum of 4%. soft-start the ssflt pin combines a programmable soft-start ramp for self-starting applications with a fault indicator. if either the v cc or the run pin voltages are below their thresholds, the ssflt pin is internally grounded. when both of these voltages rise above their thresholds, the ssflt pin is released and current flows out of the pin into an external capacitor. as the capacitor charges from 1v to 3v, the duty cycle of the gate drivers increases linearly from 0% to 70%, with a switching frequency set by a resistor from fsuv to ground. the ltc3766 should begin sending pulses and take control of the duty cycle before the soft-start pin reaches 3v; however, if the voltage reaches 3.5v, the linear regulator turns off to avoid excessive power dissipation in the linear regulator pass device. with the linear regulator off, the supply will soon drop below the v cc falling uvlo threshold, and the LTC3765 will fault and restart. direct flux limit in active clamp forward converters, it is essential to es - tablish an accurate limit to the transformer flux density in order to avoid core saturation during load transients or when starting up into a pre-biased output. although the active clamp technique provides a suitable reset voltage during steady-state operation, the sudden increase in duty cycle caused in response to a load step can cause the transformer flux to accumulate or walk, potentially lead- ing to saturation. this occurs because the reset voltage on the active clamp capacitor cannot keep up with the rapidly changing duty cycle. this effect is most pronounced at low input voltage, where the voltage loop demands a greater increase in duty cycle due to the lower voltage available to ramp up the current in the output inductor. traditionally, transformer core saturation has been avoided both by limiting the maximum duty cycle of the converter and by slowing down the loop to limit the rate at which the duty cycle changes. limiting the maximum duty cycle helps the converter avoid saturation for a load step at low input voltage since the duty cycle maximum is clamped; however, transformer saturation can also easily occur at higher input voltage where the maximum duty cycle clamp is ineffective. limiting the rate of duty cycle change in the loop to a point at which the active clamp capacitor can sufficiently track the change in duty cycle results in a very poor transient response of the overall converter. furthermore, this technique is not guaranteed to prevent transformer saturation under all operating conditions. neither of these traditional techniques will prevent the transformer from saturating when starting up into a pre- biased output, where the duty cycle can quickly change from 0% to 75%. the LTC3765 and ltc3766 implement a new unique system for monitoring and directly limiting the flux accumulation in the transformer core. during a reset cycle, when the ac- tive clamp pmos is on, the magnetizing current is directly measured and limited through a sense resistor in series with the pmos source. when the pmos turns off and the main nmos switch turns on, the LTC3765 generates an accurate internal estimate of the magnetizing current based on the sensed input voltage on the run pin and transformer core parameters customized to the particular www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 11 3765f operation core by a resistor from the r core pin to ground. the mag - netizing current is then limited during the on-time by this accurate internal approximation. unlike previous methods, the direct flux limit directly measures and monitors flux accumulation and guarantees that the transformer will not saturate, even when starting into a pre-biased output, without compromising transient response. additional protection features the LTC3765 contains additional features to protect the circuit in the event of a persistent abnormal condition. overcurrent and overtemperature monitors ensure reliable operation even in abnormal conditions. the overcurrent monitor is implemented with an external sense resistor in series with the source of the primary nmos. when the differential voltage between the current- sense pins, i s + and i s C , exceeds 150mv, the primary nmos is immediately turned off and a fault is initiated. the internal overtemperature monitor is set at 165c, with 20c of hysteresis. this is helpful for limiting the temperature of the dc/dc converter in the event of a failure or abnormal condition. if the internal temperature exceeds this level, switching immediately stops and a fault is flagged. fault indicator a fault is initiated when any of the following conditions are encountered: overcurrent trip, overtemperature trip, communication loss with the ltc3766, v cc falling below its uvlo threshold, or the run pin falling below its threshold. the ssflt pin is used to indicate these faults, to communicate the fault in a polyphase system, and to optionally lockout on a fault. when a fault occurs, switching stops immediately and the ssflt pin is rapidly pulled up to above 6v as an indicator. the ltc3766 will detect that switching has stopped and will also fault and restart. as soon as the fault clears, the voltage on the ssflt pin will slowly discharge to allow time for the ltc3766 to prepare for a restart. when the ssflt voltage reaches 0.7v, the pin is momentarily grounded, and the soft-start sequence begins again. a fault can optionally be locked out by adding a 5.6v zener diode from ssflt to ground. this will inhibit the restart until the ssflt pin is externally grounded, the diode clamp is removed, or the input supply collapses. in a polyphase ? application, the ssflt pins of the LTC3765s should all be tied together. this not only ensures that all of the LTC3765 phases begin their open-loop start-up simul - taneously, but also provides a means for communicating a fault condition. if one LTC3765 detects a fault, it pulls the combined ssflt node to above 6v. when the voltage rises above 5v, the other LTC3765s detect this and stop switching until the common ssflt pin has discharged. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 12 3765f applications information run pin resistor selection normal operation is enabled when the voltage on the run pin rises above its 1.25v threshold. as shown in figure?3, the run pin is typically used with an external resistive divider as an accurate undervoltage lockout (uvlo) on the v in supply. a 5a current is pulled by the run pin when it is below its threshold that, when combined with the value chosen for r1, increases the uvlo hysteresis beyond the internal minimum of 4%. when used in this manner, the values for r1 and r2 can be calculated from the desired rising and falling uvlo thresholds by the fol - lowing equations: r1 = v in(rising) ? 1.042 ? v in(falling) 5a r2 = 1.2 ? r1 v in(falling) ? 1.2 a 1nf capacitor in parallel with r2 is recommended to filter out noise coupling from the high slew nodes to the run pin. be aware that the absolute maximum voltage on the run pin is 12v. therefore, the following relationship between the maximum v in voltage expected and the falling v in uvlo threshold must be satisfied: v in(max) < 10 ? v in(falling) run/stop control can also be implemented by connect - ing a small nmos to the run pin as shown in figure 3. turning on the nmos grounds the run pin and prevents the LTC3765 from running. the run pin is also used to sense the input voltage for the direct flux limit. a resistive divider from v in must be connected to the run pin for proper operation of the direct flux limit. linear regulator the linear regulator eliminates the long start-up times associated with a conventional trickle charger by using an external nmos to quickly charge the capacitor con - nected to the v cc pin. the typical configuration for the linear regulator is shown in figure 4. the ndrv pin sinks up to 1ma of current through r ndrv to regulate the voltage on v cc . the minimum value of r ndrv can therefore be computed from: r ndrv > v in(max) ? 8.5v + v th ( ) 1ma where v th is the threshold voltage of the external nmos. r1 r2 v in run/stop control (optional) run sgnd LTC3765 3765 f03 figure 3. resistive voltage divider for v in uvlo and optional run/stop control r ndrv c vcc v in ndrv v cc sgnd LTC3765 3765 f04 figure 4. typical linear regulator configuration www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 13 3765f applications information the maximum value of the r ndrv resistor is limited by the 10a bias current pulled by ndrv that is required to power the internal linear regulator circuit. when the v cc supply is above a minimum voltage that is a function of the mosfet threshold, an internal charge pump provides all of the ndrv bias current; however, when v cc is below this voltage, the charge pump is not active and the ndrv resistor must supply this current. thus, a maximum value of r ndrv for the charge pump start-up can be calculated as: r ndrv < v in(min) ? 1.6v th ? 1.2v 20a these two equations result in a wide range of values for r ndrv . for many applications, a 100k resistor will satisfy these requirements. the rate of charge of v cc from 0v to 8.5v is controlled by the LTC3765 to be approximately 35s regardless of the size of the capacitor connected to the v cc pin. the charging current for this capacitor can be approximated as: i c1 = 8.5v 35s c 1 the external nmos should be chosen so that the i c1 capacitor charging current in the equation above does not exceed the safe operating area (soa) of the nmos. excessive values of c1 are unnecessary and should be avoided. typically values in the 1f to 10f range work well. a standard 3v threshold nmos should be used when possible to better tolerate a high voltage start-up transient; however, a logic-level nmos may be used for applications that require low voltage start-up. since the nmos is on continuously only during the brief start-up period, a small sot-23 package can be used. if an 8.5v to 14.5v supply is available in the system that can be used to power v cc , the linear regulator is not needed and should be disabled by tying ndrv to v cc . the external supply should be connected to the v cc pin through a series diode if the ltc3766 is configured to overdrive v cc when it begins switching. low input voltage start-up the minimum value of r ndrv is further constrained if low voltage (v in < 10v) start-up is required. in this application, the previous equation for the maximum value of r ndrv must be satisfied to start the charge pump. additionally, the charge pump current flows through r ndrv to raise the ndrv voltage above v in so that the external mosfet can be fully enhanced. r ndrv therefore needs to be large enough that the limited charge pump current can raise the ndrv voltage to this level. lower threshold logic-level mosfets are preferred for low voltage start-up not only because the mosfet requires a lower ndrv voltage above v in , but also because the charge pump current increases as the ndrv-v cc difference decreases, which is approximately the mosfet threshold. for a given threshold voltage, r ndrv should be chosen so that it meets the following relationship, keeping in mind that the previous equation for the maximum value of r ndrv must also be met. r ndrv > v th(max) 5 ? v th(max) ? ? ? ? ? ? ? 100k www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 14 3765f applications information in this equation, v th is the maximum threshold voltage of the external mosfet. table 1 below shows typical values of r ndrv for common input voltage ranges. table 1. typical r ndrv values v in range v th(max) r ndrv range typical r ndrv 8v to 36v 2v 70k to 180k 125k 36v to 72v 4v 60k to 1.4m 150k setting the overcurrent limit the overcurrent limit for the LTC3765 is principally a safety feature to protect the converter. the current that flows in series through the transformer primary winding and the primary switch is sensed by a resistor (r sense ) connected between the source of the switch and ground. the voltage across this resistor is sensed by the i s + and i s C pins. if the difference between i s + and i s C exceeds 150mv, the LTC3765 immediately turns off the primary nmos and, if ssflt is not grounded, faults. the overcurrent comparator is blanked for approximately 200ns after pg goes high to avoid false trips due to noise. choose the overcurrent trip current i trip to be less than the maximum pulsed drain current rating of the primary nmos but greater than the sum of the peak inductor current at full load and the current required to charge the output capacitor at start-up, reflected through the transformer. the sense resistor value, r sense , can be calculated from the 150mv trip threshold and the primary-side trip current from the following equation: r sense = 150mv i trip the r sense resistor should be verified to have sufficient margin over the maximum operating current of the con - verter, which typically occurs at start-up into a full load. in a self-starting application at full load, the linearly increas - ing duty cycle determined by the soft-start capacitor (c ss ) ramps the output voltage with a fixed rate independent of the output capacitor value. larger output capacitance requires a proportionally larger charging current to main- tain the output voltage ramp rate. since additional output capacitance is generally distributed through a system and may not be exactly known, the sense resistor and soft- start capacitor should be chosen with sufficient margin to ensure that the overcurrent comparator does not trip on start-up. an upper bound for the available current to charge the output capacitor can be calculated as shown in the following equation: i chg < 150mv r sense ? n s / n p ? 1.4 i load(max) where n s /n p is the turns ratio of the transformer and the factor of 1.4 accounts for the typical 40% ripple current in the inductor. to ensure that the overcurrent comparator does not trip on start-up, the soft-start capacitor should be chosen so that only a fraction of the charging cur - rent calculated above is available to charge the output capacitor. using 10% of the maximum charging current generally allows for sufficient margin. this establishes a lower bound on the soft-start capacitor value, which can be computed from: c ss > 600 ? 10 ?9 ? v in(max) ? n s / n p c out 0.1? i chg ? ? ? ? ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 15 3765f r fl r fl c fl r sense primary nmos pg i s + i s ? LTC3765 3765 f05 figure 5. overcurrent sense filtering applications information where c out is the output capacitor value and v in(max) is the maximum input voltage. the soft-start capacitor value should be in the range of 10nf to 1f. do not use a value less than 10nf. the soft-start capacitor also determines the relative timing of the output voltage rise and the ltc3766 bias supply rise. the value chosen should be verified with the equations in the following self-starting start-up sec- tion to ensure that the bias supply rises before the output voltage is close to the regulation point. care should be taken with the routing of the i s + and i s C traces to avoid noise pickup. the traces should be kelvin- sensed off of the sense resistor and routed right beside each other on an inner layer of the pcb. avoid routing near high voltage, high slew rate nodes such as the drain of the primary nmos and the drain of the active clamp pmos. depending on pcb layout and the shielding of the traces going to the i s + and i s C pins, it is sometimes necessary to add a small amount of filtering as shown in figure 5. typically, values of r fl = 100 and c fl = 200pf to 1nf will provide adequate filtering of noise pickup without significantly degrading the overcurrent response time. self-starting start-up when starting up, the LTC3765 begins switching in an open-loop fashion to supply power to the secondary side ltc3766. when the ltc3766 has adequate bias voltage and has met other conditions for start-up, it begins sending both duty cycle information and power through the pulse transformer connected to the in + /in C pins. the LTC3765s start-up switching frequency is set by a resistor from fsuv to ground. since the internal oscilla - tor is only used in start-up, the frequency accuracy is not critical; however, avoid setting the frequency excessively low, as this will cause high currents in the transformer and inductor. to minimize the impact on the transition due to the duty cycle handoff from the LTC3765 to the ltc3766, this frequency should be set to the approximately the same frequency as the ltc3766. the frequency set resistor (r fs ) value can be selected using the following equation: r fs = 6.2 ? 10 9 f sw ? 4.5k table 2 shows standard 5% resistor values of r fs for common switching frequencies. table 2. standard r fs resistor values for common frequencies frequency r fs value 150khz 36k 200khz 27k 250khz 20k 275khz 18k 350khz 13k www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 16 3765f applications information the internal oscillator generates a ramp that is compared with the voltage on the ssflt pin to generate a duty cycle. the internal oscillator has an offset that prevents switch - ing until ssflt reaches approximately 1v. when v cc is undervoltage or the run pin is below its threshold, the ssflt pin is internally grounded and the drivers therefore do not switch. when start-up conditions have been met, the ssflt pin is released and a current is sourced out of the pin to charge an external capacitor connected from ssflt to ground. initially, a 60a current is sourced out of the pin; how - ever, this current is reduced to approximately 4a when pg begins switching. the 60a initial current reduces delay due to charging the external capacitor to 1v, where switching begins. during the open-loop start-up, the output voltage rises much more quickly at high line than at low line for a given duty cycle ramp rate. this has the potential to overvolt - age the output before the ltc3766 has begun switching, particularly at no load. to avoid this situation, the 4a soft-start current is modulated by the run pin voltage, which monitors v in through a resistive divider. when the run pin voltage increases from 1.3v to 3.75v, the soft- start current decreases from 4a to 1.6a. as the external soft-start capacitor gradually charges from 1v to 3v, the duty cycle increases linearly from 0% to 70%. for ssflt voltages above 3v, the duty cycle is clamped at approximately 70% to allow for adequate active clamp reset time. when the ssflt voltage reaches 3.5v, the voltage is held and the linear regulator is turned off. the pg and ag gate drivers will continue to switch at 70% duty cycle and the v cc supply will decrease until it reaches its falling undervoltage lockout threshold. at that point, the LTC3765 will fault, turn on the linear regulator, and gradually reset the ssflt capacitor for a restart attempt. in most applications, the ltc3766 is biased from a peak charge circuit from an auxiliary winding of the main transformer. this configuration is shown in figure 6. since the LTC3765 open-loop start-up powers both the peak charge circuit and the output voltage, the primary design constraint on the soft-start capacitor value is to ensure that the output does not overvoltage before the ltc3766 has adequate bias to take control. a good rule of thumb is to select the soft-start capacitor so that the ltc3766 has adequate supply voltage before the output voltage has risen to half of its regulation point. for the peak charge circuit of figure 6, choose the value of c pk based on the capacitance required to bias the ltc3766. then choose the auxiliary winding turns ratio n a /n p to give a peak charge voltage at minimum v in of approximately 30% more than the required v cc of the ltc3766. figure 6. peak charge circuit for biasing the ltc3766 in a self-starting application pg n p n s n a ? ?? v out v in c out l 3765 f06 fg nmos body diode sg nmos body diode ltc3766 v aux c pk d pk r pk www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 17 3765f applications information a lower bound on the primary-side soft-start capacitor (c ss ) value was previously calculated in the overcurrent section to ensure that the overcurrent comparator does not trip on start-up into a full load. the value should generally be in the range of 10nf to 1f. choosing too small of a value for c ss could potentially charge the output voltage too quickly at no load or cause an overcurrent trip when starting into full load. choosing too large a value will cre- ate additional delay in the start-up, during which time the linear regulator will be providing the current to switch the primary nmos. extremely long start-up times should be avoided to avoid excessive power dissipation in the linear regulator pass device. a value of 33nf is a good starting point for most applications. the soft-start capacitor value should be verified by compar - ing the time for the peak charge circuit to deliver adequate bias to the ltc3766 to the time that the output voltage rises to half of its regulated value. the time until the ltc3766 receives bias and takes control can be approximated by: t bias 10 3 ? r eq ? c pk ? c ss + 150s where r eq is the sum of r pk and the series resistance of diode d pk . the time for the output voltage to reach half of its regulated value can then be estimated by the following equation, where v out is the final regulated output voltage: t out 10 4 ? c ss 2 v out / 2 ( ) 2 l ? c out ? f sw v in(min) ? n s / n p ( ) 2 ? ? ? ? ? ? ? ? 1/3 the above equation assumes that there is no load cur - rent, which is the worst-case condition for output voltage rise. if t out is less than t bias , then the soft-start capacitor value should be increased. note that these equations are approximations and the actual times will vary somewhat with circuit parameters. gate drivers the active clamp gate driver (ag) and the primary switch gate driver (pg) are in-phase, with a programmable overlap time set by the delay pin. traditionally in active clamp drivers, the ag driver must be level-shifted as shown in the circuit in figure 7a to drive the active clamp pmos gate from approximately v d to Cv cc + v d , where v d is the forward voltage drop across the schottky diode d ag . a silicon diode can be used instead of a schottky barrier diode; however, the forward voltage of the diode does subtract from the available gate drive of the active clamp pmos. this is particularly important at the minimum v cc uvlo falling threshold. the resistor, r ag , ensures that the active clamp pmos is off when not being driven. the active clamp level-shift circuit components can be chosen with few constraints. the time constant formed by r ag and c ag should be designed to be substantially longer than the switching period of the controller. a 0.1f capacitor for c ag and a 10k resistor for r ag result in a 1ms time constant, which provides suf- ficient margin for the 75khz to 500khz frequency range available in the ltc3766. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 18 3765f applications information alternatively, the active clamp pmos source can be returned to the v cc supply bypass capacitor, as shown in figure?7b. in this configuration, the level-shift circuit comprised of c ag , d ag and r ag is not needed. the ag output drives the gate of the pmos between v cc and ground. unlike the configuration in figure 7a, the main transformer leakage current spike and magnetizing current return to the v cc bypass capacitor. the v cc capacitor should be increased to prevent excessive ripple on the supply and a low impedance plane should be used to route v cc . the ripple on the v cc capacitor (c vcc ) due to the magnetizing current can be approximated by the following equation: ? v cc = v out n p / n s ( ) 6.8 ? c vcc ? l mag ? f sw 2 1? v out n p / n s ( ) v in(max) ? ? ? ? ? ? in general, a 4.7f capacitor is a good choice for most application circuits when the active clamp current is returned to v cc . direct flux limit in active clamp forward converters, it is essential to es - tablish an accurate limit to the transformer flux density in order to avoid core saturation during load transients or when starting up into a pre-biased output. although the active clamp technique provides a suitable reset voltage during steady-state operation, the sudden increase in duty cycle caused in response to a pre-bias output or a load step can cause the transformer flux to accumulate or walk, potentially leading to saturation. this occurs because the reset voltage on the active clamp capacitor cannot keep up with the rapidly changing duty cycle. this effect is most pronounced at low input voltage, where the voltage loop demands a greater increase in duty cycle due to the lower voltage available to ramp up the current in the output inductor. the LTC3765 and ltc3766 implement a new unique system for monitoring and directly limiting the flux accumulation in the transformer core. during a reset cycle, when the active clamp pmos is on, the magnetizing current is sensed by a resistor (r mag ) connected to the source of the pmos. the voltage across this resistor is sensed by the i smag pin. both the traditional and alternative configurations for the active clamp driver, shown previously in figures 7a and 7b, are supported. in the traditional configuration, if figure 7a. traditional ag and pg driver configuration figure 7b. alternative ag and pg driver configuration ?? 3765 f07a v in primary switch nmos active clamp pmos pg ag main transformer c clamp i smag d ag c ag r ag c sn r sn r mag ?? 3765 f07b v in primary switch nmos active clamp pmos pg ag v cc main transformer c clamp c sn r sn c vcc i smag r mag www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 19 3765f applications information the voltage on the i smag pin is less than C1v, the active clamp pmos is turned off. similarly for the alternative configuration of figure 7b, if the voltage on the i smag pin is less than (v cc C 1v), the active clamp pmos is turned off. the i smag pin therefore directly monitors and limits the magnetizing current to prevent core saturation in the negative direction. choose the magnetizing current sense resistor value to limit the transformer saturation current (i sat ): r mag = 1v i sat where the saturation current is calculated from the maxi - mum flux density (b max ), area of the core in cm 2 (a c ), number of turns on the primary (n p ), and magnetizing inductance (l mag ) from the following formula: i sat = b max ? a c ? n p 10 8 ? l mag for a transformer designed for 2000 gauss operating flux density, which is typical for a ferrite core, set b max to 2700 gauss to keep sufficiently far from saturation over tempera - ture. for the pulse pa08xx series power transformers used in the typical applications section, a c = 0.59cm 2 . for the pulse pa09xx series power transformers, a c = 0.81cm 2 . when the nmos is on, the magnetizing current and reflected inductor current are both flowing through the nmos. the inductor current is generally much larger than the mag- netizing current, which makes the magnetizing current difficult to measure directly. therefore, when the nmos is on the LTC3765 internally replicates the magnetizing current based on transformer core parameters, the voltage on the i smag pin at the end of the previous reset cycle, and the sensed input voltage on the run pin. the run pin must be connected to a resistive divider from v in to ground for proper operation of the direct flux limit. at the end of the reset cycle, the voltage on the i smag pin is sampled and held internally. this voltage is an ac - curate measurement of the magnetizing current. when the nmos turns on, an internal ramp proportional to the run pin voltage divided by the r core resistor increases the internal replicated magnetizing current. if this internal voltage exceeds 1v (or v cc + 1v for the alternative ag configuration of figure 7b), then the nmos is turned off to prevent core saturation. when the nmos is turned off due to a direct flux limit, the secondary-side switch node falls. the ltc3766 detects this prematurely falling switch node and turns off the forward gate to allow the transformer core to reset. this switch node behavior is indistinguishable from a primary-side shutdown; therefore, if the switch node falls prematurely for 19 consecutive cycles, the ltc3766 concludes that a primary-side shutdown has occurred and will fault. choose r core based on the run pin divider network and the transformer core parameters: r core = r2 r1 + r2 b max ? a c ? n p 0.030 ? ? ? ? ? ? ? 2k ? where r1 and r2 comprise the divider network on the run pin, with r1 from v in to the run pin and r2 from the run pin to ground. b max is typically 2700 gauss for a transformer designed to operate at 2000 gauss, a c is the area of the core in cm 2 , and n p is the number of turns on the primary winding of the transformer. the internal approximation of the magnetizing current is linear, which is accurate if the transformer flux density is kept sufficiently far from saturation. as the flux density approaches saturation, the magnetizing inductance of the transformer decreases and the magnetizing current increases rapidly. depending on the particular core proper - ties, it may be necessary to additionally decrease b max in the equations above. www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 20 3765f applications information in a resonant reset application, the active clamp is re - placed by a single reset capacitor. in this configuration, the transformer core is reset every cycle and is less likely to saturate; however, the transformer can still saturate during certain transient conditions. the direct flux limit can also be configured to prevent core saturation in this application. connect the r mag sense resistor in series with the ground side of the resonant reset capacitor and use the equation above for r core to prevent saturation in a forward converter with resonant reset. the direct flux limit may be disabled by tying i smag to ground and floating the r core pin; however, disabling the direct flux limit leaves the application circuit open to transformer saturation and is not recommended. active clamp capacitor the active clamp capacitor, c clamp , stores the average reset voltage of the transformer over many cycles. the voltage on the clamp capacitor is generated by the transformer core reset current, and will intrinsically adjust to the optimal reset voltage regardless of other parameters. the voltage across the capacitor at full load is approximately given by: v cl = v in 2 v in ? 1.15 v out ? n p / n s ( ) n p /n s is the main transformer turns ratio. the factor of 1.15 accounts for typical losses and delays. when pg and ag are low, the bottom side of the clamp capacitor is grounded, placing the reset voltage v cl on the swp node in figure 1. when pg and ag are high, the topside of the capacitor is grounded, and the voltage on the bottom side of the capacitor is Cv cl . therefore the voltage seen on the capacitor is also the voltage seen at the drains of the pg and ag mosfets. as shown in figure 8, the v cl voltage has a minimum when the converter is operating at 50%. for a given range on v in , therefore, the maximum clamp voltage (v cl(max) ) will occur either at the minimum or maximum v in , depending on which input voltage causes the converter to operate furthest from 50% duty cycle. the maximum v cl voltage can be determined by substituting the maximum and minimum values of v in into this equation and selecting the larger of the two. in order to leave room for overshoot, choose a capacitor whose voltage rating is greater than this maximum v cl voltage by 50% or more. typically, a good quality (x7r) ceramic capacitor is a good choice for c clamp . also, be sure to account for the voltage coefficient of the capacitor. many ceramic capacitors will lose as much as 50% of their value at their rated voltage. figure 8. active clamp capacitor voltage vs duty cycle duty cycle (%) 20 active clamp voltage normalized to 50% duty cycle 1.3 1.4 1.5 1.2 1.1 40 60 30 50 70 80 1.0 0.9 1.6 3765 f08 www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 21 3765f applications information in addition to voltage rating, another design constraint on c clamp occurs because of the resonance between the magnetizing inductance of the main transformer with the clamp capacitor. the magnetizing inductance l mag and c clamp form a high-q resonant system that results in a sinusoidal ripple on the capacitor voltage. to avoid the problems associated with this resonance, always use an rc snubber in parallel with the clamp capacitor as shown in figures 7a and 7b. choose values for the clamp capacitor and the snubber components according to the following equations, where f sw is the frequency set by the ltc3766 fs pin: c clamp = 1 2l mag ? 4 2 ? ? f sw ? ? ? ? ? ? 2 c sn = 6c clamp r sn = 1 1? v out v in(min) ? n p n s ? ? ? ? ? ? l mag c clamp be careful to account for the effect of voltage coefficient for both c sn and c clamp to ensure that the above relationship is maintained. in addition to dampening the resonance of the active clamp, the rc snubber also minimizes the peak voltage stress seen by the primary-side mosfets and reduces the effect of this lc resonance on the closed-loop transient response. setting the gate drive delay the active clamp gate driver (ag) and the primary switch gate driver (pg) switch in-phase, with a programmable overlap time set by the delay pin. the pg falling to ag falling delay (t dag ) is fixed at 180ns since the timing of this edge has little impact on efficiency. the ag rising to pg rising delay (t dpg ) is critical for optimizing efficiency and must be set in conjunction with the ltc3766 forward gate and synchronous gate delays. refer to the ltc3766 data sheet for the procedure to determine the optimal delay times for a particular application. the primary gate delay time is set by a resistor from the delay pin to ground, according to the following equation: r delay = t dpg ? 45ns ( ) ? 1k ? 9.5ns in a system where the active clamp is not desired, for example in a forward converter using resonant reset, this delay can be set to a minimum by grounding the delay pin. maximum duty cycle during the delay time between ag rising and pg rising, power is not transferred from the input supply to the output supply. in most forward converter systems, the maximum on-time is artificially limited by the delay, which then drives a trade-off between the optimal delay time and the maximum achievable duty cycle. the LTC3765 and ltc3766 implement a unique system in which the pg and fg rising delays are reduced as the demanded www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 22 3765f duty cycle approaches maximum duty cycle. this allows for greater input voltage range variation over traditional forward converters. be cautious with component selection when designing with high duty cycles. recall that the voltage on the drain of the primary switch is equal to v in /(1-d), where d is the duty cycle. this voltage increases dramatically as the duty cycle approaches 100%. the ltc3766 limits the maximum duty cycle to 79% in order to reset the transformer core without excessive voltage stress on the primary switch. pulse transformer the pulse transformer that connects the ltc3766 pt + / pt ? outputs to the LTC3765 in + /in ? inputs functions as the communication link between the secondary-side controller and the primary-side gate driver, as shown in figure 9. refer to the ltc3766 data sheet to determine the turns ratio and volt-second specifications for the pulse trans- former. keep in mind that the amplitude of the signals on the in + and in C pins should be in the range of 4v to 15v to ensure proper operation. the 1f and 0.1f capacitors in series with the pulse transformer of figure 9 are for blocking and restoring the dc level of the signal. these values are appropriate for most LTC3765/ltc3766 applications. bypassing and grounding the LTC3765 requires proper bypassing on the v cc supply due to its high speed switching (nanoseconds) and large ac currents (amperes). careless component placement and pcb trace routing may cause excessive ringing and undershoot/overshoot. to obtain the optimal performance from the LTC3765: a. use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. remember that the LTC3765 switches greater than 2a peak currents and any significant ground drop will degrade signal integrity. b. mount a bypass capacitor as close as possible between the v cc pin and ground plane. c. plan the power/ground routing carefully. know where the large load switching current is coming from and going to. maintain separate ground return paths for the signal pins and the output power stage. d. keep the copper traces between the driver output pins and the load short and wide. e. solder the exposed pad on the back side of the LTC3765 package to the ground plane. the exposed pad is inter - nally electrically connected to the sgnd pin; however, rated thermal performance will only be achieved if the exposed pad is soldered to a low impedance ground plane. ? ? 0.1f 1f n 3765 :n 3766 in + in ? LTC3765 3765 f09 pt + pt ? ltc3766 figure 9. pulse transformer connection applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 23 3765f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev c) msop (mse16) 0910 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref www.datasheet.co.kr datasheet pdf - http://www..net/
LTC3765 24 3765f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0711 ? printed in usa related parts typical application 36v-60v to 14v at 25a isolated 350w bus converter part number description comments ltc3766 secondary side synchronous forward controller direct flux limit, multiphase capable, works in conjunction with LTC3765 ltc3705/ltc3726 isolated synchronous no opto 2-switch forward controller chip set suitable for medium power 24v and 48v input applications lt1952/lt1952-1 isolated synchronous forward controllers suitable for medium power 24v and 48v input applications ltc3723-1/ltc3723-2 synchronous push-pull and full-bridge controllers high efficiency with on-chip mosfet drivers ltc3721-1/ltc3721-2 nonsynchronous push-pull and full-bridge controllers minimizes external components, on-chip mosfet drivers ltc3722/ltc2722-2 synchronous isolated full bridge controllers suitable for high power 24v and 48v input applications sgnd pgnd gnd pgnd ltc3766 sw sg i s ? i s + run 10nf 220pf 100pf 1f d1 +v in ?v in 33nf 27.4k 100 11k 66.5k 2.43k 68f 16v: sanyo 16tqc68m d1-d2: zhcs506 d5: bas21 l1: vishay ihlp4040dzer1r8m11 l2: coilcraft ser2814l-472kl q1-q3: bsc190n15ns3 q4-q7: bsc057n08ns3 t1: pulse pa0956nl t2: pulse pa0510nl t3: ice ct102-100 (1:100) ssflt 15.0k 60.4k 604 150k 10k 27.4k 3765 ta02 13.7k rcore fs/uv 14k 10k irf6217 q1 q2 q3 0.22f 250v 2.2f 100v 3 2.2f 100v 0.68 1/8w 4.22 1/8w 432 delay in ? v cc pt + fb mode ss i s ? pt ? fgd sgd fs/sync i pk ith v sec phase v s ? regsd v s + run in + ndrv fdc2512 ag pg 100 es1pd 100 100 4m 1w 165 1/8w 1.00k 1/8w 5.1k 1w 10nf 200v 33nf 200v t1 t3 i s + +v in 36v to 60v l1 1.8h 3t q4 q5 q6 q7 +v out 14v 25a ?v out +v out +v out 5t ismag +v in 2.2nf 250vac 4.7nf 0.1f t2 2.5:2 1nf d2 1f 3.3nf i s + d5 v cc ndrv fg v in 4.7f npo 33nf i s + 1nf LTC3765 0.1f 100k 1/8w 1nf 68f 16v 4 22f 16v 4 ?? ? ? ?? l2 4.7h es1pd + fcx491a efficiency 36v 60v 95.2% at 25a 95.4% at 25a www.datasheet.co.kr datasheet pdf - http://www..net/

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